My term project for the course ELEC 402: Introduction to VLSI Systems was an open-ended CMOS design of a state machine of our choosing. For my state machine I decided to create a bubble level or “spirit level” that can be used to level things horizontally.
I captured my progress in a series of reports and a short video on my LinkedIn. This post is a more in-depth discussion of my project, what I did, and how I did it.
My open ended project had these requirements:
Come up with an idea for an FSM and implement it in a hardware description language
Create an HDL test bench using immediate or concurrent assertions
Synthesize into an RTL design using a library with timings
Verify and analyze timing by testing the synthesized design with our test bench
Use automated layout tools to create a physical design of the FSM
Simulate the physical design to verify that the RTL synthesized correctly (directed testing)
In this projects I accomplished these goals and one extra one: I also synthesized and tested the design on an FPGA to verify it’s functionality in the real world.
For my FSM I chose to implement a “bubble level”, also called a “spirit level”. The general idea is that accelerometers/IMUs can be as effective, and possibly even more effective than a bubble inside a glass tube for leveling items. At the very least they are probably more accurate.
The HDL design started with some rough-draft high-level functional diagrams which were beautified for the reports:
The FSM for this project was written in SystemVerilog, and synthesized and simulated with Icarus Verilog. The IP was generated with the Efinix Efinity IDE.
The test-bench logic tests a subset of the functions of the FSM. It tests:
Resetting the FSM
Sending a request to the I2C block
Waiting for responses appropriately
Validating responses from the I2C block
Outputting to the LEDs
Identifying I2C read and write errors
It doesn’t test or permute all of the possible state machine outputs and inputs, but it does a good enough job to test the basic functionalities which is good enough for a class project. For larger systems I would use formal verification techniques instead.
After test-bench validation the top-level design was synthesized and the bit-stream was generated and uploaded to the Efinix Xyloni FPGA development board. I set up the circuit on a bread-board by soldering some pin-headers to the dev board and connected some LEDs, as well as the MPU 6050. The design was first run at a very slow clock speed, then the clock was increased to the full 50MHz. There were some errors at this stage, but they all had to do with the configuration of interface and PLL blocks of the FPGA rather than the design. At this point I had a functioning prototype that could be used to level things!
Cadence RTL Synthesis Flow
At this point I continued the project by using Cadence to go through the rest of the RTL synthesis flow to continue turning the FSM into a layout. I configured Cadence Encounter to map the FSM (and only the FSM) to the OpenCell library in the 15nm FreePDK technology using a TCL script. The result was a mapping to 170 elements taking up about 67um^2.
Timing was also verified with Cadence at this step. For the clock, the timing constraint was set to 200MHz, simulation speed to 100MHz, while the target execution frequency was set to a measly 50MHz. At this technology level these values should be easily achievable. The large margin is so that if someone wants to overclock the design 2x they can (the I2C controller has a default operating frequency of either 100MHz or 50MHz). Timing tests passed in the SS domain.
Standard Cell Place and Route Design Flow
Now that we have completed the RTL synthesis flow and verified the design, I moved onto the standard place and route design flow to create the physical layout of the chip.
Now, one minor gotcha for this section. Due to technical reasons the lab course was not able to provide us with the 15nm layout files in time for our project to continue. At this point we had to resort to falling back to the OpenCell library in the 45nm FreePDK technology instead of the planned 15nm. This means that the previous section was redone for the 45nm library before moving on with the place and route. With such a simple design as this it did not effect the performance much.
For as simple as this project was, it was an exciting introduction to the world of CMOS VLSI. With Moore’s law coming to an end, our “free-lunch” speedups will begin to be constrained by physical limitations. We will be forced to think harder about the algorithms we are running and be forced to design new, more efficient hardware to run them. I predict like Moore’s law, we will see a exponential growth in the quantity of unique hardware designs in the near future.
If you wish to view the source code you can download it here. The top-level folder structure is arranged by progress through the project and includes additional homework handed in as part of the course.